The present invention relates generally to plasma etching and, more particularly, to plasma planarization of semiconductor device layers.
As integrated circuit geometries increase in complexity and decrease in dimensions to below one micron, it becomes increasingly important to provide component layers with smooth or planar surface topographies. Planar surfaces are necessary to insure acceptable step coverage, reduce reflections during photolithography, and, in general, improve product yields. Planar surfaces are especially important in MOS technologies where initial topographies are often extremely rough. For example, where a metallic or conductive path is applied to a semiconductor substrate, the sidewalls and edges of that path typically present unacceptable steps. These steps would often inhibit proper application of additional device layers.
To reduce sidewall angles and soften edges, previous fabrication processes have included high temperature "reflow" techniques. The substrate and glass thereon would be heated to temperatures where the glass softens and starts to melt. The substrate, however, maintains its stability at these temperatures. Unfortunately, reflow techniques have often proved unsatisfactory where metal is used. To insulate these paths, oxide layers are typically applied between them. These oxide layers substantially conform to the underlying surface topography. Thus, subsequent paths applied directly to the oxide would not have a planar base surface. Without a planar base surface, designing complex, multi-layer circuits becomes extremely difficult. Attempts to apply reflow techniques to the oxide layers are not successful. Temperatures high enough to soften the oxide and cause it to flow into and fill surface steps also cause underlying metal paths to melt or peal off adjacent layers or alloy with the silicon. This results in silicon surface pits and catastrophic device failures. Further, such high temperature processing will generally enlarge device dimensions and promote poor feature size control which subsequently causes loss of device packing density.
Recently, low temperature plasma etching techniques for smoothing rough and irregular surface topographies have been developed. These are often referred to as "plasma planarization" or "plasma filing". As seen in the sectional view of FIG. 1, plasma planarization typically involves the use of a sacrificial layer 10 which is applied over rough topography 20 of insulating layer 30. Rough topography 20 may, for example, result from conformity of insulating layer 30 to metal path 40 formed on insulative layer 50 of substrate base 60. Prior research and experimentation have been directed toward achieving a planar surface 15 on sacrificial layer 10. This multi-layered product is subjected to plasma etching in a gas environment to completely remove sacrificial layer 10 and portions of insulating layer 30. Sacrificial layer 10 is etched away at the same rate as the material of insulating layer 30. As a result, the topography of relatively smooth surface 15 can be replicated on the surface insulating layer 30 without detrimentally affecting metal path 40.
Such plasma planarization techniques have been used to smooth surfaces of several materials, including polysilicon, nitrides, and various glasses. A variety of sacrifical layers have also been used, including photoresists, polyimide, and nitrides. Unfortunately, while previous plasma planarization techniques may be suitable for fabrication of some larger, less detailed integrated circuits, they do not produce surfaces which are sufficiently planar for many smaller and more complex circuit devices.
Surface roughness and irregularities remaining after such plasma planarization are largely the result of minute steps and depressions in surface 15 of sacrificial layer 10. These steps and depressions arise because the materials employed in sacrificial layer 10 typically have at least some minor conformity to the underlying topography of insulating layer 30. This conformity is reflected, although in diminished form, in the topography of surface 15. Conformity of sacrificial layer 10 is especially important where the underlying topography consists of recesses and projections having a wide variety of dimensions and where sacrificial layer 10 is relatively thin. It has been suggested to increase the thickness or height of sacrificial layer 10 above insulating layer 30 to achieve greater planarity of surface 15. However, increasing the thickness of sacrificial layer 10 causes significant increases in the planarization processing time and expense.
Further difficulties also arise with the relatively narrow processing constraints of these prior techniques. The ratio of the etch rates of the sacrifical layer to the underlying insulating layer must, as nearly as possible, be unity if the topography of surface 15 is to be properly replicated. Even the smallest deviation from a unity ratio is considered undesirable.
It is therefore an object of the present invention to provide an improved method of controlling surface topography.
Another object is the provision of an improved method of plasma planarizing surface topography of semiconductor device layers.
Still yet another object is to provide a method of planarization which may be applied sequentially to various layers of a semiconductor device during the fabrication of that device without adversely affecting the underlying layer.
Yet another object is to provide a method of plasma planarization, for surface topography of various different heights and dimensions, having a short processing time.
An even further object is to provide a method of plasma planarization which can be repeatedly reworked to planarize a given surface.
Still another object is the provision of a method of plasma planarization having relatively enhanced processing latitudes.
These and other objects of the present invention are attained in the provision of a method of plasma planarization of the surface topography of a substrate layer wherein a sacrificial layer, having an etch rate substantially different from the etch rate of the substrate layer, is applied to the surface topography of that substrate layer. The sacrificial and substrate layers are then plasma etched to remove the sacrificial layer and portions of the substrate layer. The ratio of substrate to sacrificial layer etch rate can be controlled to compensate for non-planar surface features of the sacrificial layer such that the resulting substrate surface topography is planar. Control of this etch rate ratio is accomplished by selecting appropriate materials forming the sacrificial layer for a given plasma environment and by selecting the appropriate plasma environment for a given material forming the sacrificial layer.
The etch rate ratio necessary to planarize a rough surface topography is solely a function of the material forming the sacrificial layer and the thickness of that layer, rather than a function of the height of surface projections. The sacrificial layer is preferably formed from a low viscosity, organic photoresist which at least covers the underlying surface topography. Typical etch rate ratios to achieve surface planarity of the substrate layer range from 1.4 to 10.0 in plasma environments of gaseous CHF.sub.3 and O.sub.2 for example. Since sacrificial layer can be relatively thin, short planarization processing times are achievable. Using this plasma etching technique of selecting the etch rate ratio to be a non-unity value, a variety of different surface topographies can be sculptured simultaneously. This planarization process may be applied to succeeding layers during semiconductor device fabrication without adversely affecting the underlying layers.
Further objects, features, and advantages of the present invention will become more apparent from the following description when taken with the accompanying drawings which show, for purposes of illustration only, several embodiments in accordance with the present invention.